Of the conventional digital video tape recorders, the most pertinent prior art relevant to the present invention is disclosed in, for example, the Japanese Laid-open Patent Publication No. 61-271671. In the specification of this publication, the control of an error flag during a slow-motion reproduction in the digital video tape recorder or the like is discussed. Hereinafter, this prior art will be described sequentially.
Hitherto, in the digital video tape recorder, a reproducing head traverses some recorded tracks during a high speed reproduction in which the tape transport speed is higher than that during the recording and, therefore, reproduced data consist of fragmentary data over a plurality of fields. A picture reproduced during the high speed reproduction, that is, a high-speed reproduced picture, is obtained by writing those fragmentary data into a buffer memory and then reading them out therefrom. When the reproducing data are so reproduced fragmentarily, data in all of the addresses in a memory will not be altered and the data which have been read out remain stored in the memory without being updated. Accordingly, the previous reproducing data are outputted in the form as they stand and are subsequently mixed with the current reproducing data, resulting in deterioration in the quality of reproduced pictures. In view of this, use has been made of a first flag memory adapted to be supplied with addresses identical with those in the buffer memory so that the flag can be initialized, (i.e., "1" is written) immediately after the data and the flag have been read out. Also, when the data are written in the buffer memory, a decision is made by a first error correcting decoder in the previous stage whether or not the data are correct ones and, since a flag indicative of the correctness or incorrectness of the data is outputted, only the data represented by the flag indicating the correctness are written in the buffer memory and, at the same time, "0" is written in a first flag memory when the flag indicates the correctness. By so doing, the flag read out from the first flag can distinguish whether they are the previous reproducing data or whether they are the current reproducing data. The previous reproducing data recognized by this flag can be revised by a second error correcting decoder in the rear stage of the buffer memory or by a revising circuit disposed in a stage rearwardly thereof.
The operation of the digital video tape recorder of the above described construction which takes place during the slow-motion reproduction will now be described. During the slow-motion reproduction, the tape transport speed is lowered as compared with that during the recording and a track is traversed several times to reproduce the data. However, unlike that during the high speed reproduction, a single track is traced several times while slightly sequentially displaced and, therefore, most of the data recorded on the tracks remain stored in the buffer memory in which only the reproduced, correct data have been written. Since the time during which the data remain stored in the memory corresponds to the reduction in tape transport speed (for example, twice in the case of the speed being 1/2 of the speed during the recording or three-times in the case of the speed being 1/3 of the speed during the recording), the same image data are read out from the buffer memory repeatedly over some fields during that time. Because of this, although the output from the first flag memory correctly represent either the previous reproducing data or the current reproducing data as far as the first reading is concerned, all of the flags are initialized simultaneously with the first reading and, therefore, the flag will be "1" indicative of the previous reproducing data, which have already been read out, during a second reading despite that the current reproducing data are to be read out during the second reading. Once this occurs, all of the data read out during the second reading will be in error and the second error correcting decoder and/or the revising circuit will operate erroneously to such an extent that a favorable slow-motion picture can no longer be reproduced.
In order to avoid the foregoing problem, and according to the specification referred to above, use has been made of a second flag memory disposed in a rear stage with respect to the first flag memory so that a flag outputted from the first flag memory can be written into the second flag memory simultaneously with the first reading, and also of a switching circuit for switching over between two flags, which are an output from the first memory flag and an output from the second flag memory, so that the output of the first flag memory can be selected at the time of the first reading, but the output of the second flag memory can be selected at the time of the second or subsequent reading. With this arrangement, the data read out during the second or subsequent reading can be prevented from being processed as the previous reproducing data and, by inputting an output of the switching circuit to the second error correcting decoder, a reading side (the second error correcting decoder) can read out a written flag ("0") at all times. Thus, since neither the second error correcting decoder nor the revising circuit will operate erroneously, a favorable slow-motion picture can be reproduced. The foregoing is a summary of what has been disclosed in the specification referred to above.
According to the specification referred to above, use has been made of the first flag memory and the second flag memory to accomplish the slow-motion reproduction. However, in the present invention, a method is suggested to accomplish a reproduction of favorable slow-motion pictures, similar to those obtained during normal reproduction, without utilizing the second flag memory.